Regviz

Espressif Systems /ESP32-S3 /SENSITIVE /CORE_0_PIF_PMS_CONSTRAIN_6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CORE_0_PIF_PMS_CONSTRAIN_6

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/SENSITIVE/CORE_0_PIF_PMS_CONSTRAIN_6#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER

Description

Core0 access peripherals permission configuration register 6.

Fields

CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT

Core0 access bt permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0

Core0 access i2c_ext0 permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0

Core0 access uhci0 permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST

Core0 access slchost permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT

Core0 access rmt permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT

Core0 access pcnt permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC

Core0 access slc permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC

Core0 access ledc permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP

Core0 access backup permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB

Core0 access bb permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0

Core0 access pwm0 permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP

Core0 access timergroup permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1

Core0 access timergroup1 permission in world1.
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER

Core0 access systimer permission in world1.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data